1. Technical Field
The present invention is related to hardware description languages. More particularly, the present invention provides multi-level or single strength signal detection in a hardware description language (HDL), such as Verilog, that does not easily provide for such detection.
2. Related Art
The current Verilog core standard does not provide any way to test for the specific strength of a signal. One solution to this problem is the use of the Verilog Programming Language Interface (PLI) standard. As known in the art, PLI provides a mechanism for interfacing Verilog programs with programs written in the C language, and for accessing the internal databases of a Verilog simulator from a C program. PLI is used for implementing system calls which would have been hard to do otherwise (or impossible) using the Verilog syntax. To this extent, PLI provides a way to extend the functionality of a given Verilog simulator that supports the PLI (as described in the IEEE 1364-1995 Verilog standards document).
A major drawback to using the PLI is that it is very cumbersome. To test the specific strength of a signal, for example, a C compiler is needed, and a custom C function must be written to perform the signal strength detection. The custom C function must then be linked (statically or dynamically) with a user's specific Verilog simulation tool executable, and then the user's Verilog HDL must be coded to make use of the newly written PLI routine.
There is a need, therefore, for a reusable Verilog module that is capable of performing signal strength detection.